1. Field of the Invention
The present invention relates to a semiconductor memory. It is particularly related to a nonvolatile semiconductor memory and a data programming method thereof.
2. Description of the Related Art
Inter-cell spacing of semiconductor memories has been decreasing at approximately 30% per annum through evolutions toward high integration and miniaturization architectures. With nonvolatile semiconductor memories having a plurality of memory cell transistors, each encompassing a first conductive layer (a floating gate electrode), a second conductive layer (a control gate electrode) and an inter-electrode dielectric sandwiched in between the first and second conductive layers, it is possible to store data in memory cell transistors by storing electric charges in respective conductive layers, which are made of, for example, polycrystalline silicon layers, kept in a floating state. As can be understood in a cross sectional view cut along the word line direction of a miniaturized nonvolatile semiconductor memory, since first conductive layers belonging to adjacent cell columns oppose each other across a device isolation film sandwiched in between the adjacent cell columns, “inter-column coupling” occurs between the first conductive layers belonging to adjacent cell columns due to capacitive coupling between the opposing side surfaces of these mutually opposing first conductive layers. The device isolation films sandwiched in between the adjacent cell columns may implement shallow trench isolation (STI) architecture, for example.
As the nonvolatile semiconductor memory becomes scaled down, the mutually facing area of first and second conductive layers becomes smaller. However, it is necessary to ensure a sufficient capacitance between first and second conductive layers through the inter-electrode dielectric. In other words, achievement of required area for inter-electrode dielectric in a three-dimensional structure becomes impossible as a result of the reduced inter-cell spacing, and it becomes necessary to use an insulating film with a higher dielectric constant than before as the inter-electrode dielectric to achieve required capacitance.
However, the inter-column couplings causes disturbance in the memory cell performances if a high dielectric is used as the inter-electrode dielectric. For example, because the conductive coupling between the first conductive layers belonging to adjacent cell columns becomes significant due to the transport of mobile carriers through a high dielectric for the inter-electrode dielectric, the inter-column coupling increases. Japanese Patent Application Laid-open No. 2001-168306 proposed a structure for suppressing the inter-column coupling.
Furthermore, the effect of inter-column coupling becomes noticeable since capacitive coupling between the first conductive layers increases owing to the employment of high dielectric for the inter-electrode dielectric.
Therefore, in a miniaturized nonvolatile semiconductor memory, as the inter-cell spacing decreases, the inter-column coupling drastically increases between a “written cell” retaining electric charges and an “erased cell” not retaining electric charges. For example, as shown in FIG. 2A, if an even-numbered cell column is programmed (written) and verified, and then an odd-numbered cell column is similarly programmed (written) and verified as shown in FIG. 3B, a threshold voltage Vt for the first verified even-numbered cell column increases due to the inter-column coupling, exceeding the target threshold voltage distribution illustrated in FIG. 3A, thereby causing erroneous programming.